Abstract
Time to digital converters (TDCs) are widely used in particle physics and medical imaging to determine the relative arrival time of photons and other particles. Vernier TDCs are one of the most attractive options due to their power consumption efficiency and their small footprint. We present our newly patented innovative architecture of cascaded-stage Vernier TDCs comprised of a feedthrough reference oscillator. This architecture lead to successive Vernier measurements that result in a lower number of cycles for the same dynamic range to resolution ratio (DRRR), leading to reduced conversion time and lower jitter. To validate this architecture, a test chip was designed in 0.18~弮m TSMC technology, integrating four types of cascaded Vernier TDCs with an increasing number of stages. The performance of the chip was assessed using a modular test platform specifically designed for TDCs. For comparison purposes, all TDCs were tested with a LSB of 50~ps and a dynamic range of 20~ns. The experimental results demonstrate the highest gain in performance between 1 stage Vernier and 2 stage Vernier TDCs with the precision improved from 36~ps~rms to 21~ps~rms, the maximum number of turns from 110 to 25 counts and the dead time, from 266.4~ns to 76.5~ns, on average. Adding Vernier stages is only relevant for a higher DRRR. Therefore, the 3-stage and 4-stage Vernier TDCs also show performance gains, but improvements are limited.
