Abstract
The current choice of the interconnect metal in integrated circuits is copper due to its higher electrical conductivity and improved electromigration reliability in comparison with aluminum. However, with reducing feature sizes, the resistance of copper interconnects (lines) increases dramatically. Greater resistance will result in higher energy use, more heat generation, more failure due to electromigration, and slower switching speeds. To keep pace with the projected planar transistor density, the first challenge is to identify the dominant factors that contribute to the high interconnect resistance. Here we directly measure individual grain boundary (GB) resistances in copper nanowires with a one-to-one correspondence to the GB structure. The specific resistivities of particular GBs are measured using four-probe scanning tunneling microscopy (STM) to establish a direct link between GB structure and the resistance. High-angle random GBs contribute to a specific resistivity of about 2510-12 Ωcm2 for each boundary, while coincidence boundaries are significantly less-resistive than random boundaries. Thus, replacing random boundaries with coincidence ones would be a route to suppress the GB impact to the resistivity of polycrystalline conductors. Acknowledgement: The research was supported by the Division of Scientific User Facilities, U. S. Department of Energy.
